Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method for Wiring Using Pt And Ti Over an Insulating Layer, Compatible With a Self-Aligned Silicide Process

IP.com Disclosure Number: IPCOM000101858D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 90K

Publishing Venue

IBM

Related People

Dally, AJ: AUTHOR [+4]

Abstract

A process is described in this article whereby metal deposited in a blanket on a wafer to form self-aligned silicide (over the gate polysilicon and diffusions in an FET application) can also be patterned to provide wiring with benefit both to circuit density and process flexibility.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Wiring Using Pt And Ti Over an Insulating Layer, Compatible With a Self-Aligned Silicide Process

       A process is described in this article whereby metal
deposited in a blanket on a wafer to form self-aligned silicide (over
the gate polysilicon and diffusions in an FET application) can also
be patterned to provide wiring with benefit both to circuit density
and process flexibility.

      The use of Pt-Ti wiring over SiO2 insulating regions permits
connecting Si (or PtSi-TiSi) regions formed over SiO2 in
semiconductor devices.  The section of silicon wafer 1 shown in Fig.
1 has two doped regions 3 and 4 embedded in it.  In addition, the
substrate contains SiO2 regions 2, 7, and 8.  The SiO2 region 2
serves to insulate the polycrystalline silicon (poly) region 5 from
the substrate 1 whereas poly region 6 is in contact with both the
substrate 1 and SiO2 region 8.  It remains to have a suitable contact
material, e.g., PtSi, formed over the exposed Si regions 3, 4, 5 and
6, and to connect the Si regions 4 and 6 together.

      Referring to Fig. 2, a blanket deposit of Ti is first applied
to the Fig. 1 structure in a thin layer 9 (100-200 angstroms thick),
followed by a layer 10 of Pt about 500 angstroms thick.  A suitable
annealing heat cycle will then cause the Pt and Ti over Si regions 3,
4, 5 and 6 to react and form PtSi and TiSi over these regions but
to remain unreacted over SiO2 regions 2, 7 and 8.  Note:  the Ti
layer 9 promotes adhesion of the Pt layer 10 and the Pt layer
inhibits undesired oxidation of the Ti layer.  Unreacted PtSi-TiSi
regions in Fig.  2 are designated 15, 16, 17 and 18.  The next step
in the disclosed process is based on the fact that the etch rate in
aqua regia of Pt exposed to oxygen is 10 to 15 times slower than that
of unoxidized Pt. PtSi-TiSi regions are also relatively unaffected by
aqua...