Browse Prior Art Database

Shallow Trench Formation Using Polysilicon Trench Refill

IP.com Disclosure Number: IPCOM000101864D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Bennett, RS: AUTHOR

Abstract

This article concerns a process for producing shallow and deep trench structures in the same cell on high density VLSI chips, using deposition and planarization steps common to each structure.

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Shallow Trench Formation Using Polysilicon Trench Refill

       This article concerns a process for producing shallow and
deep trench structures in the same cell on high density VLSI chips,
using deposition and planarization steps common to each structure.

      Shallow trench structures are commonly fabricated using a
recessed oxide (ROI) for the isolation.  While such structures using
ROI are relatively simple to fabricate, they may be sensitive to
defect generation at the corners of the shallow trench, and the
bird's beak formed during ROI processing takes up a great amount of
area.  The disclosed process uses PST, rather than ROI isolation,
with chemical-mechanical polishing for planarization in both the deep
and shallow trench.  This approach, as illustrated in Figs. 1-5,
avoids severe oxidation of the silicon substrate while allowing for
the simultaneous performance of the refill and polishing steps
necessary to planarize both deep and shallow trenches.  This
procedure also eliminates several additional process steps necessary
to generate the shallow trench.

      Figs. 1-5 illustrate how the deep and shallow trenches are
fabricated together.  In Fig. 1, the shallow trench 1 is formed by
RIE during the etch process presently employed for defining
registration marks.  The combining of the two mask levels acts to
make unnecessary thirteen process steps used in the conventional ROI
process.  Also identified in the drawing are the substrate 2, an n+
...