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Sub-Micron Channel Length CMOS Technology

IP.com Disclosure Number: IPCOM000101872D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 6 page(s) / 192K

Publishing Venue

IBM

Related People

Dally, AJ: AUTHOR [+4]

Abstract

By means of processes documented in this article the well-known CMOS technology is implemented to obtain (Image Omitted) sub-micron channel length (N0.3 um) CMOS devices with an excellent control of break-down and punch-through.

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This is the abbreviated version, containing approximately 40% of the total text.

Sub-Micron Channel Length CMOS Technology

       By means of processes documented in this article the
well-known CMOS technology is implemented to obtain

                            (Image Omitted)

 sub-micron
channel length (N0.3 um) CMOS devices with an excellent control of
break-down and punch-through.

      Two separate but related process descriptions are provided in
this disclosure, one for a conventional semi-recessed oxide
(semi-ROX) iso- lation structure and the other for a full ROX
isolation structure. Either process starts with a p+ Si substrate 1
with a p-epi Si layer 2 on top, as shown in Fig. 1.  The epi
layer is N3 ohm-cm resistivity and 2.5-3.0 um thick at the process
start.  The relative shallowness of this layer makes it easier to
implement a trench or other ROX type isolation because the trench
depth is relatively small for this thickness of epi.  At this point
the isolation/N-well formation sequence can employ either the
conventional semi-ROX or full ROX isolation structure.  We will begin
with the semi-ROX method, as follows:

      With semi-ROX, a relatively thin (N150 angs.) pad oxide of SiO2
3 is first grown on epi layer 2 over which N1500 angs. of Si3N4 4
are deposited.  These thicknesses are chosen to reduce "bird's
beaking" effects.  A ROX level resist (mask) 5 is then used to
pattern the Si3N4/SiO2, as shown in Fig. 2.  The ROX level pattern is
transferred into the Si3N4/SiO2 by RIE (Reactive Ion Etch).  The
resist 5, however, is left in place.  The "block field" mask layer 6,
which is made thicker, is then directly superimposed on 5, which has
been prehardened purposely by UV, etc.  The two resist levels, 5 and
6, are shown in Fig. 3, where the "block-field" mask 6 acts to offset
the boron field implant 7 (used for channel stopping) away from the
p-channel device region 8 (the "N-well").  This offset acts to avoid
shorts that could form at the edge of the ROX should the "N-well"
phosphorus not be able to diffuse far enough under the field oxide.
Masks 5 and 6 are then stripped and ROX oxidation is performed,
following which the Si3N4 4 is stripped and the N-well resist level 9
mask is put on the wafer, as shown in Fig. 4.  (It should be noted
that an offset is not necessary here 10 because a later n+
source/drain implant will provide contact to the N-well 8.) This
implant is done at a high enough energy, i.e., 360 KeV, to place the
N-well junction sufficiently close to the p+ substrate 1/epi 2
interface (see Fig. 1), and can be implemented by using doubly
ionized phosphorus at 180 KeV if necessary.  The p+ substrate edge
will move during the hot processing steps.  A drive-in step is used
to spread the N-well 8 as shown in Fig. 5.  The extra protection
afforded by the block-field mask 6 (see Fig. 3) should also be noted
(Fig. 5).  An n+ source/drain implant, designed to enter where shown
by 11 in Fig. 5, will provide contact to the N-well later, making
oth...