Browse Prior Art Database

Staged Doubled Railed Directory LRU

IP.com Disclosure Number: IPCOM000101874D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 28K

Publishing Venue

IBM

Related People

Clark, LJ: AUTHOR

Abstract

Disclosed is a cache directory scheme which minimizes the number of directory accesses required to process a request.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Staged Doubled Railed Directory LRU

       Disclosed is a cache directory scheme which minimizes the
number of directory accesses required to process a request.

      Cache directories in the past have been managed using an LRU
(least recently used) algorithm.  This involved appending some bits
to the directory entries for each congruence class.  These bits would
be read out during the directory search cycle and, depending on
whether the requester got a 'Hit' or not, they would be updated in an
ensuing cycle.  For applications with heavy directory activity, this
extra directory access will result in an appreciable performance
degradation.

      This directory scheme eliminates this extra directory access by
staging the access of the LRU arrays after the directory search
cycle.  Results of the directory search are used to determine if the
LRU arrays are to be read out (in case of directory miss) or updated
(in case of directory hit).  Since the LRU bits are 'doubled railed',
there is no longer any need to read them prior to updating to
maintain good parity.

      This scheme can also be applied to the directory change arrays
which are updated for store requests that hit and read out for fetch
requests that miss.