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Tight Tolerance Polysilicon Resistor Process

IP.com Disclosure Number: IPCOM000101875D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 136K

Publishing Venue

IBM

Related People

Acocella, JE: AUTHOR [+2]

Abstract

This article describes how tight tolerance, high-value sidewall resistors are obtained by utilizing a process compatible with existing advanced transistor fabrication practices. Emitter (or base) polysilicon is employed in forming the sidewall resistor.

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This is the abbreviated version, containing approximately 52% of the total text.

Tight Tolerance Polysilicon Resistor Process

       This article describes how tight tolerance, high-value
sidewall resistors are obtained by utilizing a process compatible
with existing advanced transistor fabrication practices.  Emitter (or
base) polysilicon is employed in forming the sidewall resistor.

      High-resistance resistors, useful in certain I/C circuits,
require large amounts of VLSI chip surface area as well as separate
processing steps for their formation.  The disclosed integrated
process provides tight tolerance, high-value resistors through the
use of procedures compatible with advanced transistor fabrication
practice.  Emitter (or base) polysilicon employed for the sidewall
resistor structures gives a high resistance per unit length because
of its small cross-section.  Resistors produced by this means, for
example, employ mandrel heights ~3000 angstroms and sidewall widths
~1800 angstroms to obtain sheet resistances ~220 ohms/square, i.e., a
resistivity ~9x10-3 ohms-cms.  with a 3 sigma spread of 4.0% -10.0%
across the wafer, and from wafer to wafer.

                            (Image Omitted)

      Figs. 1-6 illustrate the general procedure followed after a
normal emitter sidewall CVD (chemical vapor deposition) to obtain
high value resistors.  Note that photoresist (P/R) shown in all mask
drawings are not to scale.  Referring to Fig. 1 and the area above
the resistor region 1 of the device, a mandrel mask 2 is placed on
deposited layers of 1400 angstroms TEOS 3, 800 angstro...