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High-Speed Restore Method for Differential Cascode Voltage Switch

IP.com Disclosure Number: IPCOM000101882D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR [+3]

Abstract

A dense and high speed method is shown for restoring a class of semiconductor logic known as differential cascode voltage switch or DCVS logic.

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High-Speed Restore Method for Differential Cascode Voltage Switch

       A dense and high speed method is shown for restoring a
class of semiconductor logic known as differential cascode voltage
switch or DCVS logic.

      DCVS logic gates have internal nodes which may retain the
previous cycle's logic state and cause charge sharing problems
resulting in glitches on the true/complement outputs. These glitches
may cause logic error signal propagation. Prior art teaches the use
of restore diodes to charge internal nodes to a value of Vdd-Vt.
Although effective for low speed applications, it is not adequate for
high-speed cycle operation. Also, this technique requires a large
layout area. Described is a new method for restoring DCVS gates in
high-speed applications. It is particularly useful in critical high
performance logic paths.

      Referring to the figure, the new restore technique is shown
restoring a 4-input DCVS XOR gate but applies to all DCVS-type gates.
Restore devices T24 through T30 are shown gating VDD by clock phase
precharge (PC). This restores all internal nodes to VDD, thus
providing maximum leakage immunity and protection against charge
sharing (glitching). In addition, restore time is greatly shortened
over the prior art, permitting fast cycle time operation. The
prior-art arrangement puts a large load on PC, slowing down the
restore and enable operation.  In the logic restore example shown, a
P-device connected to each internal node is th...