Browse Prior Art Database

Charge Pump

IP.com Disclosure Number: IPCOM000101883D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Ebler, MB: AUTHOR [+3]

Abstract

A charge pump is an important element in many phase-locked loop designs. The charge pump's function is to change logic signals from the phase frequency detector into current pulses. These current pulses charge or discharge a filter which controls the voltage controlled oscillator (VCO). A charge pump has three states: a current of magnitude I going out of the circuit, a current of magnitude I coming into the circuit or no current. The duration of the current pulses is determined by the phase difference between the reference clock and the VCO. If the phase difference is very small, the required current pulses are very small, which would require fast edges on the current pulse.

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Charge Pump

       A charge pump is an important element in many
phase-locked loop designs.  The charge pump's function is to change
logic signals from the phase frequency detector into current pulses.
These current pulses charge or discharge a filter which controls the
voltage controlled oscillator (VCO).  A charge pump has three states:
a current of magnitude I going out of the circuit, a current of
magnitude I coming into the circuit or no current.  The duration of
the current pulses is determined by the phase difference between the
reference clock and the VCO.  If the phase difference is very small,
the required current pulses are very small, which would require fast
edges on the current pulse.

      Fig. 1 shows a schematic of the current switching portion of
the charge pump circuitry.  In this circuit D0 and D1, I0 and I1 are
differential pairs of logic signals. With these two sets of
differential signals there are four possible logic states.  When D0
and I0 are both high or both low, the charge pump is in the null
state with no current coming into or going out of the circuit.  When
D0 is high and I0 is low, current is coming into the circuit, and
when I0 is high and D0 is low, current is flowing out of the circuit.

      The PNP's Q1 and Q2 are matched transistors that each have a
collector current I.  This current I is mirrored with Q7 and a helper
transistor of Q8 to transistors Q9 and Q10. When D0 is high and I0 is
low, Q4 and Q5 each have c...