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Browse Prior Art Database

Support Processor Access of Memory

IP.com Disclosure Number: IPCOM000101884D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR [+4]

Abstract

In the 2032, 2564, and 3064 CPU implementations for the RISC System/ 6000 product family (see the figure), there are two ways for the CPU to access memory: the first is through normal loads and stores, the second is through diagnostic I/O operations. The diagnostic I/O operations are normal Fixed Point I/O operations with a special address range. The Storage Control Unit (SCU) will detect the special address range and the I/O load or store will access main memory. When performing I/O operations to memory, both the data and the ECC check bits are written or read. The Data Cache Unit (DCU) will generate the ECC check bits during writes operations. For writes, the data is sent from the Fixed Point (across the P-Bus) to the SCU (across the SIO-Bus) to the DCU to the memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Support Processor Access of Memory

       In the 2032, 2564, and 3064 CPU implementations for the
RISC System/ 6000 product family (see the figure), there are two ways
for the CPU to access memory:  the first is through normal loads and
stores, the second is through diagnostic I/O operations.  The
diagnostic I/O operations are normal Fixed Point I/O operations with
a special address range. The Storage Control Unit (SCU) will detect
the special address range and the I/O load or store will access main
memory.  When performing I/O operations to memory, both the data and
the ECC check bits are written or read.  The Data Cache Unit (DCU)
will generate the ECC check bits during writes operations.  For
writes, the data is sent from the Fixed Point (across the P-Bus) to
the SCU (across the SIO-Bus) to the DCU to the memory.  For reads,
the data comes from memory to the DCU to the SCU to the Fixed Point.

      The chips are designed so that an Engineering Support Processor
(ESP) can start, stop, scan, and single step the chips.  When
debugging the RISC System/6000 system, the ESP can scan out the state
of the latches.  If desired, the ESP can also modify the state of the
latches.  The ESP can read or write system memory by using this
scanning capability and some additional logic in the SCU.

      In this method of accessing main storage, the ESP will scan out
the state of the processor chips and save the state.  The ESP will
then load the SCU with a state that is equivalent to the SCU state
just after it receives a diagnostic I/...