Browse Prior Art Database

High-Speed Phase Detector

IP.com Disclosure Number: IPCOM000101886D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Deremer, RL: AUTHOR [+3]

Abstract

The phase detector (P/D) is a critical part of a phase-locked loop (PLL). A phase detector produces an output signal whose average value is proportional to the phase difference between a reference (R) and a variable (V) input signal. This output signal is filtered and sent to the input of a voltage controlled oscillator (VCO). The voltage controlled oscillator varies the frequency of the variable input. This produces a known and constant phase difference between the reference and variable inputs. This phase detector was designed to be used when the reference signal was a nonreturn-to-zero (NRZ) serial stream of data and the variable signal was an internal clock. In this application, the phase detector places the positive transition of the internal clock in the center of each data bit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High-Speed Phase Detector

       The phase detector (P/D) is a critical part of a
phase-locked loop (PLL).  A phase detector produces an output signal
whose average value is proportional to the phase difference between a
reference (R) and a variable (V) input signal.  This output signal is
filtered and sent to the input of a voltage controlled oscillator
(VCO).  The voltage controlled oscillator varies the frequency of the
variable input.  This produces a known and constant phase difference
between the reference and variable inputs.  This phase detector was
designed to be used when the reference signal was a nonreturn-to-zero
(NRZ) serial stream of data and the variable signal was an internal
clock.  In this application, the phase detector places the positive
transition of the internal clock in the center of each data bit.

      Fig. 1 shows a block diagram, timing diagram, transfer
function, and gain constant for the phase detector (P/D). The phase
detector consists of two differential positive transition D type
master slave flip-flops.

      The schematic for DFF1 is shown in Fig. 2.  DFF1 is a
differential positive transition D type master slave flip-flop with
synchronous set and asynchronous reset.  DFF1 is set (output goes
high) on each positive transition of the clock line and reset (output
goes low) when the reset line is high.  DFF1 has been modified from a
normal flip-flop to include a differential reset whose delay is
independent of the state of the clock line.  This feature improves
the linearity of the phase detector transfer function.

      The schematic for DFF2 i...