Browse Prior Art Database

Shift/Load/Hold Buffer

IP.com Disclosure Number: IPCOM000101892D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Hardell, WR, Jr: AUTHOR

Abstract

Disclosed is a means to control a first-in, first-out buffer where the data must come right out of a latch and the data needs to go directly into a latch. In this method of buffering each latch needs 3 ports. The 3 ports are the shift, load, and hold ports. The figure shows the block diagram for a four-deep shift/load/hold buffer. The latches are connected in a chain with the shift ports. New data can be loaded into any of the latches. Data from the buffer always comes from the same latch (Latch 0 in the figure). The control logic must know how many of the latches have valid data. This buffering method is simple except for the case when data is loaded and unloaded on the same cycle, especially when the buffer is partially filled.

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Shift/Load/Hold Buffer

       Disclosed is a means to control a first-in, first-out
buffer where the data must come right out of a latch and the data
needs to go directly into a latch.  In this method of buffering each
latch needs 3 ports.  The 3 ports are the shift, load, and hold
ports.  The figure shows the block diagram for a four-deep
shift/load/hold buffer.  The latches are connected in a chain with
the shift ports.  New data can be loaded into any of the latches.
Data from the buffer always comes from the same latch (Latch 0 in the
figure).  The control logic must know how many of the latches have
valid data.  This buffering method is simple except for the case when
data is loaded and unloaded on the same cycle, especially when the
buffer is partially filled.

      The figure also gives the equations for controlling the 4-deep
buffer.  These equations can be easily expanded to control deeper
buffers.  If the 3-port latches use pass-gate multiplexers (muxes) on
their inputs, then the mux delay should be negligible.  The valid
bits (V0, V1, V2, V3) can be generated by having an extra bit in each
of the latches and in the data input.  Set the extra bit in the data
input to '1' and set the corresponding input on the shift port (D1)
on Latch 3 to '0'.  The extra bit will be '1' in the latches that
contain valid data.