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Efficient Handling of Storage Operands That Cross Page Boundaries

IP.com Disclosure Number: IPCOM000101893D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 136K

Publishing Venue

IBM

Related People

Funk, MR: AUTHOR [+5]

Abstract

In a processor architecture that provides instructions that manipulate operands in storage, many of these instructions can have storage operands that may cross virtual page boundaries. A mechanism is desired that: 1. Minimizes the special handling required for operands that cross pages. 2. Provides protection from having the processor inadvertently access a new virtual page when the operand approaches, but does not actually cross the page boundary.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Efficient Handling of Storage Operands That Cross Page Boundaries

       In a processor architecture that provides instructions
that manipulate operands in storage, many of these instructions can
have storage operands that may cross virtual page boundaries.  A
mechanism is desired that:
   1.  Minimizes the special handling required for operands that
cross pages.
      2.  Provides protection from having the processor inadvertently
access a new virtual page when the operand approaches, but does not
actually cross the page boundary.

      In a processor that provides instructions that manipulate
operands in storage, some of these instructions can have storage
operands with lengths of one, two, four, or six bytes.  Many of these
instructions place no restrictions on the alignment of the storage
operands. Therefore, it is possible for the operands greater than one
byte in length to cross doubleword (eight byte) boundaries.  In order
to efficiently access these operands using its eight-byte interface
to the cache, a processor could provide the ability for the microcode
to specify a Fullword-Aligned Doubleword (FDW) fetch or store.  This
function allows eight bytes to be accessed on any four-byte boundary.
In this way, any two- or four-byte operand can be accessed using one
fetch or store regardless of the alignment of the operand. In
addition, any six-byte operand that is aligned on a two-byte boundary
can be accessed using one fetch or store.

      There are three cases that occur while using an FDW fetch or
store.
 1.  Both the operand and the FDW access do not cross a page
boundary.
      2.  Both the operand and the FDW access do cross a page
boundary.
 3.  The operand does not cross a page boundary but the FDW access
does.

      The method proposed to support the handling of storage operands
that may or may not cross virtual page boundaries is to provide an
"Allow Page Cross" flag for each storage operand used by an
instruction.  It is possible for an instruction to have multiple
storage operands that cross virtual page boundaries.  This case is
handled by providing a separate Allow Page Cross flag for each
operand.  The flag is turned on for an operand if:
      -  The operand is known to cross a virtual page, AND
      -  Both of the virtual pages are resident in main storage.

      During the execution of the instruction, if an attempt is made
to access storage across a page boundary, the Allow Page Cross flag
is checked.  If the flag is set, the page crossing is allowed.  If
the flag is not set, the part of the access up to the page boundary
is completed and the part that crosses the boundary is aborted.  In
this way, a single type of memory access can be used to access an
operand regardless of whether it crosses a page boundary, approaches
but does not cross a page boundary, or does not approach a page
boundary.

      The result of this is that no test for reaching...