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Chained Store Operations for Improved Main Store Performance

IP.com Disclosure Number: IPCOM000101897D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 112K

Publishing Venue

IBM

Related People

Eikill, RG: AUTHOR [+6]

Abstract

Disclosed is a hardware circuit to support chained store operations. Chained Stores provide optimization of Main Store performance by allowing up to 32 contiguous bytes of storage to be updated with stores as small as a single byte into the cache with the Main Store Control Unit (MSCU) concatenating them into a single store command to Main Store. This takes full advantage of the Main Store interface which was optimized for operations on blocks of data.

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Chained Store Operations for Improved Main Store Performance

       Disclosed is a hardware circuit to support chained store
operations.  Chained Stores provide optimization of Main Store
performance by allowing up to 32 contiguous bytes of storage to be
updated with stores as small as a single byte into the cache with the
Main Store Control Unit (MSCU) concatenating them into a single store
command to Main Store.  This takes full advantage of the Main Store
interface which was optimized for operations on blocks of data.

      Chained Stores provide a means of maintaining high Main Store
bandwidth while allowing the flexibility of byte stores in the
processor.  This allows the Cache accesses to be customized, for
Chained Stores provide a means of converting stores that are
optimized for Cache operation into Main Store operations that are
optimized for Main Store performance.  Chained Store allows up to 32
contiguous bytes of storage to be updated with stores as small as a
single byte into the cache.  The MSCU concatenates them into a single
store command to Main Store.

      Chain Stores allow for more efficient storage of data when
stores less than a quad-word long are performed to contiguous
locations in Main Store.  A Chain Store is a concatenation of
multiple small stores into a single store of up to 32 bytes for Main
Store.  Instead of issuing individual store commands to the Main
Store card, data from the cache bus is accumulated into a FIFO
buffer.  Special control lines (Byte Writes) to the Cache are used to
control the number of bytes stored and the alignment of the data.
When the transfers of data over the Cache bus are complete, a single
command is sent to Main Store with the data accumulated into double
words.  This allows the Main Store card to replace many of the
Read-Modify-Write operations with more efficient quad-word store
operations.

      Implementing chained stores improves the Main Store bandwidth
by allowing small stores in the processor to be handled as quad-word
stores on the Main Store Bus and Main Store Cards.  This eliminates
unnecessary Read-Modify-Write operations.

      Main Store Bus usage can also be reduced by concatenating
double- word stores into 32-byte stores.  The Main Store card can
buffer two commands of up to 32 bytes each.  Concatenating
double-word stores into 32-byte stores reduces four commands and four
data cycles to one command and four data cycles.  This optimization
of Main Store commands reduces the time in which the memory card is
busy because it cannot accept another command.  Reducing this busy
time improves the processor performance. Continued

      The following two examples show cases where performance
improvement is obtained.  The first example shows how concatenating
small stores into a single store eliminates both Main Store Bus
Cycles and unnecessary Read-Modify-Writes.
           Eight one-byte stores:
            ...