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Integrated-Circuit Module I/O Test On Simple Tester

IP.com Disclosure Number: IPCOM000101899D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 134K

Publishing Venue

IBM

Related People

English, KJ: AUTHOR [+2]

Abstract

For logic modules that have many inputs and outputs, it is desirable to allow a test system to cause the outputs to go to all possible states (high, low, and, if applicable, high-impedance) and check whether inputs are properly received.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Integrated-Circuit Module I/O Test On Simple Tester

       For logic modules that have many inputs and outputs, it
is desirable to allow a test system to cause the outputs to go to all
possible states (high, low, and, if applicable, high-impedance) and
check whether inputs are properly received.

      In many modules, especially level-sensitive scan design (LSSD)
modules, there are two inputs:  Power-On Reset (POR) and Scan Gate.
POR usually causes outputs to drive to predetermined values; it may
also cause the chip to flush its LSSD scan path to initialize latch
values.  Many chips have POR inputs that are not called POR inputs;
they may be labeled Reset, Standby, or something else, but they have
the effect of causing many or all of the output drivers to go to
predefined states.  The POR signal can thus be used to test the
values of the drivers that are set by the POR active signal.

      If the chip does a reset (flush or otherwise) during a POR
test, the output values of some drivers may be different after the
end of POR than during POR.  For these drivers, this second state can
be tested.  If the drivers are non-tristate, then both states are
tested.

      However, for tristate drivers, or for drivers where the value
after POR is the same as that during POR, additional control is
necessary.  In LSSD logic, it is often necessary to have a Scan Gate
signal that enables the LSSD control logic in the chip (usually,
forcing clock gating to pass the clock to the slave latch in an LSSD
Scan Register Latch when the slave clock and the LSSD B clock are
ORed together). During POR, this signal has no purpose, and during
LSSD scans, POR may or may not be on.  (If POR is to be on
during LSSD operations, POR must not affect the scan-out pins.)
Because the state of Scan Gate is a don't-care during POR's active
state, we can use it to expand module input/output testing.

      If both POR and Scan Gate are active, then drivers that do not
switch to a different state after POR, are to switch to a state other
than the state that POR causes without Scan Gate being active.
Drivers that do have different states after POR versus during POR,
but are tristate drivers, still require that the third state (one of
0, 1, or high-impedance) be tested; POR and Scan Gate should cause
the third state to be driven.

      Note that Scan Gate is a convenient signal to use in
conjunction with POR; it is not required.  Most input signals have no
function during POR, and most of them would be acceptable for
modifying the effect of POR.

      This combination causes most drivers to be tested in all their
output states.  Some drivers that may not be tested completely are
tristate drivers that do not drive different values during and after
POR.  These have had two states tested; a third remains to be driven.
There are several ways to approach this:  one is to choose two states
that are to be tested (say, 0 and high-impedance) and cons...