Browse Prior Art Database

Store Purge Pipeline for Mid-Range Processor

IP.com Disclosure Number: IPCOM000101903D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 136K

Publishing Venue

IBM

Related People

Eikill, RG: AUTHOR [+2]

Abstract

A design and implementation of a multiprocessor system requires overcoming a significant number of design and implementation hurdles. This article deals with the problems encountered in keeping caches coherent. It guarantees all system caches stay coherent and in all boundary conditions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

Store Purge Pipeline for Mid-Range Processor

       A design and implementation of a multiprocessor system
requires overcoming a significant number of design and implementation
hurdles.  This article deals with the problems encountered in keeping
caches coherent.  It guarantees all system caches stay coherent and
in all boundary conditions.

      Any multiprocessor implementation must solve the cache
coherence problem.  This involves guaranteeing that all caches
maintain up-to- date main store data.  Whenever one processor does a
store to a location in second processor's cache, it is a requirement
to purge the second processor's cache.  If the second processor
refetches the data, the cache line will be reloaded from main store.
Guaranteeing the store purge timings helps optimize semaphore logic
and available main store bandwidth.

      A general multiprocessor system includes:
   Main store can be shared between tasks with byte
   granularity.
   Store thru cache assumed for simplicity.
   Cache coherency maintained entirely by hardware.
   One-way associative cache with destructive store through.
   One system address bus (including I/O).
   Local two-ported cache directory with main store bus
   snooping.

      Inventions to help guarantee store purge timings:
   Store purge pipeline with guaranteed timings.
   MpSteal and store repeat to handle boundary conditions.
   Store purge of pending fetch causes directory to be
   marked invalid.
   Purge of Mp directory for store miss occurs during
   "check" cycle.

      BACKGROUND: System Address Bus. Having only one system address
bus simplifies a multiprocessor design.  It guarantees that all
stores to memory are visible to all processors.

      Local Two-Ported Cache Directory with Main Store Bus Snooping.
Each processor must check every store against his cache.  Since every
system store requires one directory read cycle, the cache directory
was made two ported.  One port is called the cache directory which is
available to the processor for fetch and store operations on every
cycle, and the other port is called the MP cache directory
(multi-processor directory) which is available on every cycle for
main store address bus snooping.  This implementation guarantees
every store can be checked against all system caches with no
performance overhead.  If a purge is required (hit in Mp directory),
the hardware initiates a purge.  The two-port directory can be
implemented by copying the directory chip.

      Semaphores.  Semaphores can be linked to the purge pipeline.
This allows them to know when the caches are up-to-date.

      DETAILS
      MP Store Purge Pipeline with Guaranteed Timings.  Every store
is read from the multi-processor directory exactly one cycle after
the address is on the main store command bus, unless another store
purge gets in the way.  If another purge gets in the way, the main
store address...