Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

# Capacitance Target Generator

IP.com Disclosure Number: IPCOM000101905D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 69K

IBM

## Related People

Anderson, HW: AUTHOR [+4]

## Abstract

This article relates to a capacitance target generator for the performance optimized placement and wiring of VLSI chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Capacitance Target Generator

for the performance optimized placement and wiring of VLSI chips.

Many physical design programs for floorplanning, placement and
wiring may be guided by capacitance targets for nets.  For this
purpose, it is important to calculate upper bounds of the net
capacitances from (real or estimated) capacitances for the physical
design, which guarantee the target cycle.  The upper bounds are
called capacitance targets.  The main problem is to calculate from
the required cycle time of a path capacitance targets for the various
nets contained therein.  To resolve this problem, equal shares of the
slack (the slack of a path being the difference between the required
and the actual signal arrival time) are distributed to each net in
the path.  As the total delay of a path is the sum of the net
delays and each net delay is multiplied by the same constant, this
method does not require information on the number of nets contained
in the path, the advantage being that each net is treated
individually.

For a given capacitance, a timing simulation is done by a
suitable tool.  The output is a slack report containing the following
information for each path and each of the associated nets.
net capacitance:    cap in pF
slack of path:      slack(path) in ns
The slack of a net is defined as the minimum slack(path) of the
various paths associated with the net.  The electrical parameters of
the output pin driving the net are known from delay equations.  For
T: slope the delay of signal propagation from a given input to the
output pin is approximated by

(Image Omitted)

delay = (k1 + k2 \$ cap) \$ T + k3 \$ cap2 + k4
\$ cap + k5    (1) where k1, k2, k3, k4 a...