Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Atomic Quad Word Fetch And Store for Pointer Updates

IP.com Disclosure Number: IPCOM000101907D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Levenstein, SB: AUTHOR [+2]

Abstract

A system using tagged pointers simplifies some operating system constricts. A tagged pointer consists of an aligned quad word (16 bytes) of data. The operating system requires that pointer updates occur "all at once". An implementation that allowed a processor to fetch a pointer containing half-new data and half-old data would require serializing all pointer operations; this requires extra instructions. The idea described allows atomic 16-byte operations with an 8-byte memory interface.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Atomic Quad Word Fetch And Store for Pointer Updates

       A system using tagged pointers simplifies some operating
system constricts.  A tagged pointer consists of an aligned quad word
(16 bytes) of data.  The operating system requires that pointer
updates occur "all at once".  An implementation that allowed a
processor to fetch a pointer containing half-new data and half-old
data would require serializing all pointer operations; this requires
extra instructions. The idea described allows atomic 16-byte
operations with an 8-byte memory interface.

      Using semaphores to protect pointer updates causes a
significant performance degradation due to the number of instructions
that reference tagged pointers.  A semaphore single threads pointer
updates.  It is also slower and causes more cross-cache thrashing.

      Atomic quad word fetch:
      -  Quad word fetch from main store:  The CPU always requests
both doublewords of a pointer at once.  If the data is fetched from
main store (cache miss), then BOTH doublewords are returned to the
processor during the cache line fill.
-  Quad word fetch from cache:  It takes two accesses to fetch a quad
word from cache.  If the first access gets a cache hit, then the
second doubleword MUST come from the same cache line.  Either
hardware must guarantee that the two doublewords are fetched in
consecutive cycles or the second fetch must ALWAYS get a cache hit
(even if a purge cycle occurred between the two f...