Browse Prior Art Database

Processor Intercommunication Register

IP.com Disclosure Number: IPCOM000101908D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 136K

Publishing Venue

IBM

Related People

Eikill, RG: AUTHOR [+6]

Abstract

All multiprocessor systems require a messaging scheme to send messages between processors. Described is a register called the Processor Intercommunications Register (PIR), including an efficient set of controls to efficiently solve the problem of sending messages between processors. A messaging scheme must cause an interrupt. In this design, that interrupt is handled by HMC.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Processor Intercommunication Register

       All multiprocessor systems require a messaging scheme to
send messages between processors.  Described is a register called the
Processor Intercommunications Register (PIR), including an efficient
set of controls to efficiently solve the problem of sending messages
between processors.  A messaging scheme must cause an interrupt.  In
this design, that interrupt is handled by HMC.

      PIR invention details:
      -  Duplicated PIR register:  This allows any processor to use
the register without issuing a cache fetch (or main store fetch if
cache miss).  The PIR is a hardware register duplicated in all
processors.
 -  Acts like a main store location:  HMC stores to the PIR as if it
were a main store location.  This allows the multiprocessing logic to
schedule bus cycles for a PIR store as if it were a normal store.
The main store bus snooping logic causes the data to be latched on
all processors. Storing to the PIR also allows use of the normal MP
locks to serialize accesses to the PIR.  Since the PIR is a register
and not a main store location, unnecessary cache purges and misses
are eliminated.
 -  PIR definition details:  The multiprocessor design provides a
special register, the PIR (processor intercommunications register),
to speed the transfer of information.  Data which is written to the
PIR of one processor is also written to the PIR of each of the other
processors.

      This design provides a new MP exception.  Some of the PIR bits
are processor ID (processor identification) mask bits.  Each bit
corresponds to one of the processors.  When a command is written to
the PIR with EXC bit equal to one, an MP exception is raised on each
processor whose ID bit is set.  To acknowledge a command, a processor
must reset its ID bit.  Resetting an ID bit is accomplished by
writing it to the PIR with the EXC bit equal to zero.

      When sending a PIR message, the processor ID bits are loaded
immediately in the sending processor.  The PIR message to the other
processors may be delayed due to main store bus traffic.  This
feature allows the sending processor to immediately reread the PIR to
wait for responses (see the figure).

      The data field in the PIR is large enough to send a virtual
address page identifier.  This allows the PIR to be used to send a
virtual address segment to be purged from the lookaside buffers of
all processors.  The data field is also used as a command extender;
the CMD field is only two bits.
 -  PIR busy detection:  If any processor has not acknowledged the
latest command in the PIR by resetting its ID bit, the PIR is busy.
If all ID bits are 0, the PIR is available.  If the sending processor
does not set its own ID bit, the PIR becomes available automatically
when the last processor acknowledges.  To retain control of the PIR
(reserve the PIR), a processor can set its own acknowledged bit so
the PIR appears busy to...