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Browse Prior Art Database

Microcode Programmable Patch Logic

IP.com Disclosure Number: IPCOM000101914D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Bruns, JJ: AUTHOR [+5]

Abstract

Described is a method of including logic in an integrated circuit chip's initial design which may be used to patch logic errors found after the chip has been fabricated. This logic, called programmed by microcode allowing designers to incorporate logic that is flexible and easy to customize to their future needs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 73% of the total text.

Microcode Programmable Patch Logic

       Described is a method of including logic in an integrated
circuit chip's initial design which may be used to patch logic errors
found after the chip has been fabricated.  This logic, called
programmed by microcode allowing designers to incorporate logic that
is flexible and easy to customize to their future needs.

      Microcode programmable patch logic consists of internal patch
circuits and the programming register.  Each internal patch circuit
maps chip inputs to chip outputs using functions that depend on the
state of certain control bits.  These control bits are in a memory
mapped I/O (MMIO) addressable register called the programming
register.  After the chip has been fabricated, microcode can select
which function each circuit will provide by simply writing to the
programming register.

      Fig. 1 shows the connection of the two main features of this
invention; the internal patch circuits and the programming register.

      The circuit in Fig. 2 can be used as a microcode programmable
patch circuit.  This circuit can provide either the latched or
unlatched version of the OR, NOR, XOR, XNOR, AND or NAND of two chip
inputs.  R1, R2, R3, R4, and R5 are bits from the programming
register, A and B are chip inputs, and C is a chip output.  R1 can
be used to immediately invert the B input.  Also, R2 and R3 are used
to select the OR, AND, or XOR of A and the output of XOR #1.
R4 can be used to invert the...