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Browse Prior Art Database

Architecture to Facilitate Card Interconnect Self-Test

IP.com Disclosure Number: IPCOM000101916D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 112K

Publishing Venue

IBM

Related People

Schoenbaum, RJ: AUTHOR [+2]

Abstract

This article describes a technique and hardware implementation that provides a fast way to bring up a processor card. Shorts and opens between the processor and application-specific integrated circuits (ASICs) connected on a bus are detected.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Architecture to Facilitate Card Interconnect Self-Test

       This article describes a technique and hardware
implementation that provides a fast way to bring up a processor card.
Shorts and opens between the processor and application-specific
integrated circuits (ASICs) connected on a bus are detected.

      During the card bring-up effort many cases of shorts and opens
on address, data, parity and control lines have been encountered.
These shorts and opens are extremely time-consuming to find in a
32-bit-wide address and data bus environment.

      The architecture disclosed herein is a combined hardware and
firmware method to automatically detect and flag shorts and opens on
a bus shared by processor(s) and ASICs.  The method utilizes ASIC
interconnection-test exception logic to allow the processor to send
and receive patterns through the ASICs input/outputs (IOs) to fully
validate the address and data paths.

      The method requires very few additional ASIC logic cells and no
additional ASIC IO pins to implement.  The implementation assumes a
minimal set of interconnections (approximately 1/10 the total
signals).  The method requires the use of an emulator or a dedicated
processor platform fixture (PRF) as described in the preceding
article.

      Each ASIC chip is assigned a unique address bit which is its
interconnection-test chip-select (ITCS).  By this method, only one
address bit must be connected between each ASIC and the processor;
that ASIC's chip select bit.  Once the ASIC's base register has been
initialized, the interconnection test function is disabled and, the
ITCS addresses become available as ordinary parts of the address map.

      To guarantee the interconnection testing, each ASIC's single
chip-select address bit should have its electrical continuity
verified to the processor along with the critical control signals
(R/W, acknowledge, AS, and clocks).  This set of four signals is in
contrast to the full 64 bits of address and data, and approximately
dozen control signals which would have to exist for card-resident
code to fully test interconnection.

      The ASIC interconnection test method configuration is shown in
functional block diagram of the figure.  In operation each ASIC is in
interconnection test mode (ITM) when its base register is in the
uninitialized state.  While in ITM, each ASIC will operate in the
following manner.  On write operations for which a given ASIC's chip
select (ITCS) is high, the ASIC will store the state of the address,
data, control and par...