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Browse Prior Art Database

In Circuit Signature Checking Device

IP.com Disclosure Number: IPCOM000101919D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Jacob, F: AUTHOR

Abstract

There is disclosed a simple and low-cost effective device to check the result of a self-test run at chip level in a machine environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 78% of the total text.

In Circuit Signature Checking Device

       There is disclosed a simple and low-cost effective device
to check the result of a self-test run at chip level in a machine
environment.

      The device can be used in a design where no simulation of the
good chip signature has been done, because it requires a huge amount
of the Central Processing Unit power.

      The device also provides an easy way of testing a chip at the
machine level, where no chip tester support is available.

      The invention provides the merging in a hardware macro of all
the functions required by self test, thus relieving the design from
complex signature extraction and compare mechanism. A go/no-go signal
is generated after the self test, which is needed for the rest of the
machine.

      Fig. 1 describes the functions performed by the macro, i.e.,
the generation of the signature, the good signature storage and the
compare operation between both of them.

      The pin functions are the following:
      - signature generator inputs: connected to latch
       chains.
 - ST pin: forces the signature generator as a shift
        register.
      - SI input of the shift register.
      - A, B clocks: clocks of the signature generator
        latches.
      - ROS write: write of the internal ROS.
      - SO: output of the shift register.
      - OK/KO result: good/no-good signal after self-test.

      Fig. 2 shows an embod...