Browse Prior Art Database

Bufferized ECL-Type Logic Circuit

IP.com Disclosure Number: IPCOM000101921D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Mollier, P: AUTHOR [+3]

Abstract

This invention relates a means of substituting the popular Emitter Follower (EF) circuit commonly used at driving the output load of a logic circuit by a new capacitively driven buffer. This drastically improves the highly loaded logical path propagation delay and also cuts the average power approximately by two.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Bufferized ECL-Type Logic Circuit

       This invention relates a means of substituting the
popular Emitter Follower (EF) circuit commonly used at driving the
output load of a logic circuit by a new capacitively driven buffer.
This drastically improves the highly loaded logical path propagation
delay and also cuts the average power approximately by two.

      The new driver is shown in the figure.  The ECL gate provides
two collector signals (OP, IP) which drive the buffer. The output
buffer is built around an emitter follower pull-up transistor (TPU)
and a common emitter pull-down transistor (TPD). The principle of
this circuit is described below.

      - OUTPUT RISE TRANSITION: The signal IP switches from
VCC-(R2+RC)xICS to VCC-RCxICS. The opposite behavior is observed on
signal OP. The transistor TEF turns off, and REF discharges the node
EF until TEF returns on.  This negative transition at node EF
produces an IC current which discharges C.  During this, the node BD;
is kept about at a constant voltage equal to -Vbe(TCL1). The
pull-down transistor TPD was off and is simply maintained off, since
the resistor RBD continues to drain a low value current through TCL1
when IC vanishes. Since TPD is kept off, the rising IP transistion
(which was the starting point) gives an efficient rise switching at
the gate output since no current is drained to VEE as it is the case
with an EF. One notices that the rise transition indeed starts when
IP node voltage is higher than VB2, since transistors TCL2 and TPU
are connected in a differential common emitter manner. This feature,
as it is seen later, is a necessary one to insure the transistor TPU
is turned...