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Current Mode Bipolar/CMOS Module-to-Module High-Speed Data Interface

IP.com Disclosure Number: IPCOM000101947D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Dreps, DM: AUTHOR [+3]

Abstract

This article describes a simple current mode interface for module-to-module communications. The basic circuit interface is shown in Fig. 1. The differential and cascode circuits are used for input and output stages, respectively. The interface lines are clamped to VREF-0.8 volts. Since there is virtually no voltage swing on these lines, the circuit is insensitive to impedance mismatch, thus eliminating terminating resistors. This reduces power consumption, and saves valuable real estate. Also reduced is coupled noise due to capacitance because of the small difference in voltage (delta V<100mV). The current swings are in the order of 2 mA. This small current reduces inductance effects. To achieve high data rates, the transistors in the differential stage are maintained in the linear region by using emitter degradation.

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Current Mode Bipolar/CMOS Module-to-Module High-Speed Data Interface

       This article describes a simple current mode interface
for module-to-module communications.  The basic circuit interface is
shown in Fig. 1.  The differential and cascode circuits are used for
input and output stages, respectively. The interface lines are
clamped to VREF-0.8 volts.  Since there is virtually no voltage swing
on these lines, the circuit is insensitive to impedance mismatch,
thus eliminating terminating resistors.  This reduces power
consumption, and saves valuable real estate.  Also reduced is coupled
noise due to capacitance because of the small difference in voltage
(delta V<100mV).  The current swings are in the order of 2 mA.  This
small current reduces inductance effects.  To achieve high data
rates, the transistors in the differential stage are maintained in
the linear region by using emitter degradation.

      The bipolar current mode interface can be extended to a current
mode CMOS interface.  This is shown in Fig. 2.  A critical point with
this design is that the voltage swing on R3 and R4 must be higher
than the threshold voltage of the FETs so that they can be fully
turned on.

      To summarize:
   Simple interface
   Gigahertz speed attainable (<1 nanosecond pulses for the
   BIPOLAR interface).
   Impedance mismatch insensitive.
   Inductance effects reduced.
   Lower power dissipation than bipolar TTL, and terminated
   ECL.
   N...