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Synchronization And Speed-Tracking Logic for Slave-Driven Transfers

IP.com Disclosure Number: IPCOM000101949D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17

Publishing Venue

IBM

Related People

Dieffenderfer, JN: AUTHOR [+2]

Abstract

This article describes logic intended for a VLSI chip for potential use on future I/O processor (IOP) cards on the AS/400* line of computers. It also describes the logic needed for speed tracking and synchronization of the DFCI tags and assumes knowledge of the DFCI architecture.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 23% of the total text.

Synchronization And Speed-Tracking Logic for Slave-Driven Transfers

       This article describes logic intended for a VLSI chip
for potential use on future I/O processor (IOP) cards on the AS/400*
line of computers.  It also describes the logic needed for speed
tracking and synchronization of the DFCI tags and assumes knowledge
of the DFCI architecture.

      The current DFCI I/O devices are run by the 6010, 6110, and
6310 IOPs.  The 6010, the oldest, is the base IOP for both the 6110
and 6310 controller.  6010 is used on both AS/400 and 9370 machines,
and the 6110 is used only on AS/400 machines.  The 6310 was a
hardware and microcode improvement to boost 6010's performance on the
9370 machines.

      The above mentioned IOPs had two main DMA channels and streamed
data across the DFCI bus at a maximum of 6.0 megabytes per second to
keep up with the 9347.  A new DFCI device adapter is needed should
any devices faster than 6 megabytes per second be used.  The method
described below depicts logic to track and synchronize the speed of
the slave with the internal clocks of the master.  The acronyms in
the drawings are defined in Table 1.

      Referring to Fig. 1 there is shown a representative digital
data processing system with IOP 7 showing the incorporation of a
Device Controller Adapter (DCA) 13.  The IOP 7 controls the transfer
of data and other information between a host processor 1 and I/O
devices 16, 17 and 18. The system may also include other IOPs, such
as IOPs 19 and 22 each connected to I/O buses 20 and 23 and I/O
devices 21 and 24, respectively.

      Fig. 2 shows the five DFCI tags and two data buses in the data
transfer states.  Select Out, Master Out and Sync Out are driven by
the master and Slave In and Sync In are driven by the slave (I/O
devices 16, 17, 18 of Fig. 1).  The sources of the A and B bus
data are shown for both device read and device write operation.

      The data rate of a DFCI transfer is controlled by the slave.
For a device read operation, the slave sends data on the A and B
buses (double octet mode) along with a Sync In pulse to the master.
The master responds by sending the slave a Sync Out pulse.  The data
sent by the slave must be valid at the leading edge of Sync In with
the architected deskew and hold time for the data.  During device
writes the master only sends data to the slave along with a Sync Out
pulse in response to receiving a Sync In pulse.  The data sent by the
master must be valid at the leading edge of Sync Out with the
architected deskew and hold time for the data.

      The concept of interlocked or streaming data transfers relates
to the DFCI tags Sync Out and Sync In during the data transfer
sequences.  Interlocked transfers require the slave or master to wait
until each Sync signal it asserts is responded to by the asserting of
the corresponding Sync signal.  In streaming transfer mode, the slave
may assert Sync In before receiving the...