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Current Switches With Speed-Up Junctions

IP.com Disclosure Number: IPCOM000101959D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

The area, power and delay time of a current switch (CS) circuit may be reduced significantly by utilizing the base-collector junction of the current source transistor in the manner described in this article.

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This is the abbreviated version, containing approximately 64% of the total text.

Current Switches With Speed-Up Junctions

       The area, power and delay time of a current switch (CS)
circuit may be reduced significantly by utilizing the base-collector
junction of the current source transistor in the manner described in
this article.

      Typical emitter-coupled logic (ECL) circuits consist of two
fixed voltage bias, Vx and Vr, as shown in Fig. 1.  By combining
these (see the Fig. 2 circuit), it is possible to obtain a faster
circuit requiring less power and chip area. The base-collector
junction diffusion capacitance Cjd (shown dotted-in in Fig. 2) of
transistor Tx is here employed to become the signal swing transistor
as well as the current source generation bias.  Since the DC current
drain to Vee is dictated by Vx and Rx, Ix is thus relatively
constant, and so the logic swing of IcRc is insensitive to the input
voltage levels.  The current source alternates from Vc and Vx during
circuit operations, while the bottom transistor Tx is shifting
between linear and saturation regions.

      By way of explanation, when input A is up and transistor Tx is
operating in the linear region, transistor T1 can shut off quickly by
swinging A below the level of Vx. When A is down and Tx is in
saturation, T1 can then be turned on abruptly by swinging A above the
level of Vx.  The diffusion capacitance Cjd of the base-collector
junction of Tx tends to hold down node x, and so speeds up the
turn-on of T1.  Fig.  3 waveform measurements show that...