Browse Prior Art Database

Dual ST506 Direct Bus Attach Hardfile Circuit

IP.com Disclosure Number: IPCOM000101997D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Hausman, KA: AUTHOR [+3]

Abstract

This article describes a circuit which allows two fixed resource hardfiles to be attached to the same personal computer bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dual ST506 Direct Bus Attach Hardfile Circuit

       This article describes a circuit which allows two fixed
resource hardfiles to be attached to the same personal computer bus.

      Typically multiple drive hardfile controllers distinguish
between the physical drives by a bit or bits located in a control
register.  This allows the software to easily select the target
device on a command basis.  The current ST506 direct bus attach (DBA)
files, as result of having integrated controllers, do not have this
capability. The drives have fixed address decodes, direct memory
access (DMA) channel controls and interrupt levels.  Previous designs
attempted to manage this by externally decoding separate address
ranges for the devices and activating one or the other chip select
based on an externally programmable control bit.  While this
technique is workable it is contrary to widely available hardware
implementations and therefore represents a software incompatibility.
The scheme disclosed herein also will add external circuitry, but in
a fashion consistent with current implementations, i.e., compatible
with existing software designs.

      This implementation will allow overlapped operations to occur
on two drives in a fashion similar to existing designs with multiple
drives connected to a single controller.  A drive may be selected via
the control register and issued a command.  The other drive may then
be selected and issued its command independently.  Whichever drive
completes its command first will raise an interrupt and the source
will be latched in the control register.  When the second drive
completes, and the first interrupt has been serviced, its interrupt
will also be latched and forwarded to the system. While concurrent
data transfers are not possible, they are typically not possible in
multi-drive controllers either. The system need only monitor the DMA
status for completion of a transfer prior to switching to the other
drive in...