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Diagnostic Interrupt Logic Testing

IP.com Disclosure Number: IPCOM000102002D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Chisholm, DR: AUTHOR [+5]

Abstract

This article describes a technique for use in a computer system which allows testing of interrupt logic without forcing interrupt conditions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Diagnostic Interrupt Logic Testing

       This article describes a technique for use in a computer
system which allows testing of interrupt logic without forcing
interrupt conditions.

      MICRO CHANNEL* architecture supports intelligent bus controller
cards.  The term intelligent bus controller implies on-card
processing capabilities for the execution of subsystem tasks,
self-testing and error diagnostics.  The on-card processor is
referred to as the local processor.

      A MICRO CHANNEL bus master interface chip set uses two
registers to generate interrupts to its local processor.  An
interrupt mask register (IMR) contains mask bits which are set by
local processor writes to allow interrupts, or cleared by local
processor writes to disable interrupts.  An interrupt status register
(ISR) contains status bits which are set by local processor writes
during diagnostics and by hardware after a direct memory access (DMA)
port transfer completion, DMA channel transfer completion, or an
attention port (AP) write from the MICRO CHANNEL.  If the
corresponding bit in the IMR and ISR register is set, the chip set
will generate an interrupt on its local bus.  The ISR register status
bits are cleared by local processor writes.

      During diagnostics, the interrupt logic can be tested by local
processor writes to the IMR and ISR registers. This allows
verification of the interrupt logic without executing a DMA port, DMA
channel, or AP operation. An example...