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Browse Prior Art Database

Subnanosecond Pulse Format Converter

IP.com Disclosure Number: IPCOM000102012D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Hoffman, DE: AUTHOR [+3]

Abstract

This article describes a circuit for generating the narrow pulse widths required for test systems used in semiconductor device manufacturing. Fig. 1 shows the typical circuit used in the past. The data signal is clocked into a master-slave flip-flop and the output is set or reset to the desired pulse width.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Subnanosecond Pulse Format Converter

       This article describes a circuit for generating the
narrow pulse widths required for test systems used in semiconductor
device manufacturing.  Fig. 1 shows the typical circuit used in the
past.  The data signal is clocked into a master-slave flip-flop and
the output is set or reset to the desired pulse width.

      When the clock pulse occurs before the set/reset (S/R) pulse
(case 1), the minimum pulse width (MPW) is limited by the output edge
speeds of the flip-flop.  The MPW occurs when the S/R pulse takes
effect as the clocked output edge reaches full amplitude.  (See Fig.
2.)

      When the S/R pulse occurs before the clock pulse (case 2), the
MPW is limited by the width of the S/R pulse and the propagation
delay of the master latch (removal of S/R signal to master latch
output).  Because the S/R pulse is level sensitive, the master output
stays S/R until the pulse goes low.  If the clock changes before the
master output changes, the slave output transition will be timed to
the transition at the master output and not the clock transition as
desired. (See Fig. 3.)

      The MPW for this second case is the larger of the two cases
and, therefore, is the area of improvement in the new circuit which
is shown in Fig. 4.  The first change in this circuit is the addition
of a pulse differentiator which creates a small positive pulse for
each rising transition of the S/R signal.  The pulse must be large
enough to allow the S/R to propagate through the latch and back to
the latch input so the latch can latch up.  Reducing the width of the
S/R puls...