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Redundancy Compare Latch

IP.com Disclosure Number: IPCOM000102014D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

In the high-density, high-end arrays, redundancy must be used to enhance the yield, and address inputs must be latched to relax the timing constraints. However, when the spare array is accessed, a delay penalty of one compare circuit stage is always incurred. This is illustrated in Fig. 1.

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Redundancy Compare Latch

       In the high-density, high-end arrays, redundancy must be
used to enhance the yield, and address inputs must be latched to
relax the timing constraints.  However, when the spare array is
accessed, a delay penalty of one compare circuit stage is always
incurred.  This is illustrated in Fig. 1.

      Since the compare circuit must drive large fan-outs and operate
in large voltage swings, the nominal delay penalty is about 200-300
ps, which amounts to over 10% of a typical array access time.  Since
the array circuits are already optimized for performance, not much
delay can be reduced by brute force power increase.

      A new redundancy compare circuit is proposed to eliminate this
delay penalty.  The revised redundancy path is shown in Fig. 2 with
the new compare circuit in Fig. 3.

      Essentially the latching function is duplicated in the compare
circuit so that the regular external address can be directly used for
compare purpose.  The Fig. 3 circuit is derived from the regular
address receiver latch, with identical resistors and current sources.
Thus voltage levels and timings in the redundancy path will be
totally compatible with those in the regular address path.

      The signal levels from the DC redundancy address are like the
regular lower cascode signal levels except for the higher up level.
The RT and RC signals uniquely determine which of the two current
switches are to be used to realize the compare...