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Extending Dram Address Space for Test and Characterization Purposes

IP.com Disclosure Number: IPCOM000102019D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Drake, C: AUTHOR [+2]

Abstract

An improved method for providing additional decode address space is described for test and characterization of dynamic random-access memories (DRAMs) for I/O bits not normally required, e.g., the output of selected internal logic states or redundancy bits.

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This is the abbreviated version, containing approximately 52% of the total text.

Extending Dram Address Space for Test and Characterization Purposes

       An improved method for providing additional decode
address space is described for test and characterization of dynamic
random-access memories (DRAMs) for I/O bits not normally required,
e.g., the output of selected internal logic states or redundancy
bits.

      Traditional schemes for increasing address space require the
addition of one full address, resulting in a doubling of decode
address space. This is usually accomplished by adding an additional
device in series with the NAND or NOR decode tree which has the
undesirable side effect of slowing down the decoder. A new method is
shown which does not make changes to the basic "on pitch" decoder.

      Through the addition of a CMOS NAND decoder for the final bit
decode ahead of the off chip driver (OCD) steering and control logic,
a 1 of 64 select is implemented utilizing 3 sets of 4 predecode lines
and a 3 input NAND "on pitch" static decoder (see the figure). The
128-bit register is decoded to steer 2 bits into the last stage of
the steering and control logic which determines whether one or both
bits are used to to decode the extended address space. To provide the
necessary addressing capability, one of the three sets of predecode
lines is driven by a 3-input AND gate versus the traditional 2 input
AND. The third input is the complementary output from the additional
address pin. When this input is high (default state), the predecoder
functions normally.  In test mode (extended address test mode), the
input reflects the complement of the additional address pin. If the
pin is high, all 4 predecode outputs are driven low, forcing all
"normal" address locations to be deselected. When the extra address
pin is low, its complement is high and all "normal" locations are
addressable.

      In...