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Address Transition Detection-Based Unclocked BICMOS Memory Design

IP.com Disclosure Number: IPCOM000102027D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 5 page(s) / 129K

Publishing Venue

IBM

Related People

Isihara, K: AUTHOR [+2]

Abstract

This article relates to a BICMOS L1 cache chip for a mainframe system. The conventional gated or clocked design approach to implement the bit-line precharging technique, which is used to speed up the differential sensing of the bit-line pairs during a read operation and also to prevent the write recovery problem, can largely compromise the performance benefits derived from the technique. The reason is that the memory clock skew must be included in the total read access and write time. The desire to eliminate this clock skew and address set-up time penalty associated with the clocked design approach prompted a new approach.

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Address Transition Detection-Based Unclocked BICMOS Memory Design

       This article relates to a BICMOS L1 cache chip for a
mainframe system.  The conventional gated or clocked design approach
to implement the bit-line precharging technique, which is used to
speed up the differential sensing of the bit-line pairs during a read
operation and also to prevent the write recovery problem, can largely
compromise the performance benefits derived from the technique.  The
reason is that the memory clock skew must be included in the total
read access and write time.  The desire to eliminate this clock skew
and address set-up time penalty associated with the clocked design
approach prompted a new approach.

      The clocked BICMOS cache design has two operational modes.
When the array clock is HIGH, the in-phase and out-of-phase outputs
of all the word address and bit address receivers are forced HIGH.
This results in the entire array being in the standby (deselected)
mode.  When the array clock is LOW, the chip can operate in the
read/write mode. Fig. 1 illustrates a clocked address receiver.
                               Fig. 1

      When the CLK is HIGH, the G output of the address gate is HIGH.
Since it is emitter-dotted with the output of the address receiver
circuit, the output of the receiver is HIGH regardless of the logical
state of the AX input.  The receiver output will respond to the input
only when the CLK is LOW.

      This clocked design approach permits the deselected array to be
precharged when the array clock is HIGH and to be read or written
when the clock is LOW.  The reason for the bit line precharging is to
speed up the differential sensing of the bit line pair during read
and to diminish the write recovery problem.
Fig. 2 - Bit Line Pair Waveform For The Clocked BICMOS Chip
Fig. 3 - Bit Line Pair Waveform For The Unclocked ECL Chip

      The above two sets of waveforms (Figs. 2 and 3) show that, in
practice, the differential sensing of the bit line pair is faster for
the clocked design than the unclocked one.

      As illustrated in Fig. 1, the address receiver circuit does not
respond to the address input until the CLK transitions from HIGH to
LOW.  Consequently, the clock skew must be included in the total read
access and write time of the cache chip.

      The clocked design approach to accomplish bit line precharging
can be counterproductive due to clock skew delay penalty associated
with this approach.  The answer is to eliminate the clock skew
dependency by using the unclocked design approach while not forsaking
the bit line precharge capability.

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