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Stacked, Single X-Tal Emitter for High-Performance Vertical PNP Transistors

IP.com Disclosure Number: IPCOM000102050D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 92K

Publishing Venue

IBM

Related People

Harame, DL: AUTHOR [+4]

Abstract

A technique is described whereby a low temperature and in-situ doped single X-tal emitter is used to make a vertical PNP transistor with improved switching performance when compared with the corresponding, separately optimized NPN transistor.

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Stacked, Single X-Tal Emitter for High-Performance Vertical PNP Transistors

       A technique is described whereby a low temperature and
in-situ doped single X-tal emitter is used to make a vertical PNP
transistor with improved switching performance when compared with the
corresponding, separately optimized NPN transistor.

      Future high-end computer systems require that bipolar
technology provide maximum performance at reduced power density.
High speeds have been attained with ECL circuits and NPN transistors,
but at the expense of increased power requirements.  However, devices
faster than 25 GHz and circuit gate delays of less than 50 ps at 2mW
and 75 ps at 1 mW are needed.  Complementary circuit designes
indicate that these objectives can be achieved with equal NPN and PNP
devices.  However, the switching performance of vertical PNP
transistors has been significantly lower than that of NPN
transistors.

      The concept described herein provides A PNP that actually
exceeds NPN performance, while retaining the integrability of the NPN
process.  The concept implements a technique of forming the emitter
by epitaxy at a very low temperature, so as to obtain an extremely
abrupt base- emitter profile. By using single X-tal materials, the
process ensures low emitter resistance.  High doping reduces the base
current to acceptable levels (b > 50 from 2D simulation).  A low
processing temperature (550R@C) of the emitter provides a thin base
profile throug...