Browse Prior Art Database

Evaluating Wafer-Level Tests by Means of Card Logic Tester

IP.com Disclosure Number: IPCOM000102055D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Lusch, RF: AUTHOR [+2]

Abstract

Disclosed is a technique that utilizes a card logic tester as a vehicle to evaluate the effectiveness of new chip-level tests. This technique allows rapid implementation and verification of various test algorithms as chip failure mechanisms are discovered.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Evaluating Wafer-Level Tests by Means of Card Logic Tester

       Disclosed is a technique that utilizes a card logic
tester as a vehicle to evaluate the effectiveness of new chip-level
tests.  This technique allows rapid implementation and verification
of various test algorithms as chip failure mechanisms are discovered.

      In general, the testing of components is accomplished in a
hierarchical manner, i.e., each time one or more processing steps are
performed on a part, it is tested again.  This means, for example,
that chips are tested at the wafer-level, than at the module level,
and again after the modules are incorporated in the next level of
packaging, which may be cards or boards.  In a perfect test
methodology, the testing at each level detects all of the failures
introduced by the previous processing step. However, it is often the
case that some failures do escape. Therefore, these problems must be
detected by later tests.

      The capabilities and flexibility of the testers for each
packaging level are different.  Implementing tests on a wafer-level
tester is straightforward, though it may be tedious.  Module-level
testers are primarily driven by patterns created by automatic test
generation and are therefore more restrictive.  For card-level
testers, high-level languages provide the ability to implement test
algorithms easily and efficiently.  When the modules are mounted
directly on boards, a specialized tester is impractical and, hence,
testing is done in a system environment.

      When...