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Interrupt Translation Circuitry

IP.com Disclosure Number: IPCOM000102061D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Eng, RC: AUTHOR [+3]

Abstract

This article describes a circuit arrangement in a personal computer (PC) system which translates an active high, edge-triggered interrupt into an active low level-sensitive interrupt.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Interrupt Translation Circuitry

       This article describes a circuit arrangement in a
personal computer (PC) system which translates an active high,
edge-triggered interrupt into an active low level-sensitive
interrupt.

      In the parallel bus architectures of personal/industrial
computers, a discrepancy can exist between different PC families'
interrupt definition.  One family's interrupt (family A) can be an
active high edge-triggered signal, whereas another family's interrupt
(family B) can be active low level-sensitive.  In the situation where
a personal/industrial computer is designed to be able to accommodate
both families' cards, a circuit is required which adapts one family's
interrupts into the other family's interrupts.

      In the family B architecture the interrupts can be defined to
be driven by open-collector gates.  This allows several devices to
use and share the same interrupt level at one time, since there is a
limited number of interrupt levels available.

      In the family A architecture, interrupt sharing can be
implemented by requiring the following:
   -    If the device does not use an open-collector driver on the
interrupt line, it must tri-state the interrupt line when it is not
using it.  When it does use the line, no other device may at the same
time.
      -    All devices which use interrupts must have three signals
within their interrupt generation mechanism:
                1)   ENABLE, which is set to enable the card to
interrupt, if it needs to, or cleared to inhibit interrupts from it.
                2)   DISABLE, which is set by any interrupt on that
level and also inhibits the card from interrupting, so that a device
that is sharing the interrupt level does not cause an i...