Browse Prior Art Database

Shadow BiCMOS Circuits

IP.com Disclosure Number: IPCOM000102064D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Chuang, CTK: AUTHOR [+2]

Abstract

Disclosed is a high-speed, low-power shadow BiCMOS circuit concept wherein the logic is performed with bipolar circuits when active and the logic state/level is maintained with CMOS circuit during standby.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Shadow BiCMOS Circuits

       Disclosed is a high-speed, low-power shadow BiCMOS
circuit concept wherein the logic is performed with bipolar circuits
when active and the logic state/level is maintained with CMOS circuit
during standby.

      It is well-known that CMOS circuits lack driving capability
while bipolar circuits need constant current to maintain the logic
level.  Conventional BiCMOS circuits with CMOS inputs and bipolar
push-pull drivers are not scalable due to the conflicting power
supply requirements.

      In the present scheme (Fig. 1), both the logic function and
output are realized with bipolar circuits for high-speed operation.
The bipolar current is switched on and off through control switches
SW1 and SW2.  A CMOS circuit is attached to the output.  By locking
the control switch SW3, the output node can be switched to either the
bipolar or the CMOS circuits.

      When clock (CLK) is 'High', SW1 and SW2 are closed and SW3 is
opened.  The input signal immediately propagates to the output
through the bipolar circuit.  At this moment, the CMOS circuit is
hanging passively at the output.  When CLK switches from 'High' to
'Low', SW1 and SW2 are opened, and SW3 is closed.  The bipolar
circuit is detached from the power supplies and the output is
floating.  However, the CMOS circuit will lock the output level,
since SW3 is closed.

      Fig. 2 depicts the schematics and timing diagram of a latch
where D is the input and Q is the output.  Q changes to the stat...