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Browse Prior Art Database

In Situ-Trimmed Fine-Grained Polysilicon Resistors

IP.com Disclosure Number: IPCOM000102083D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Comfort, JH: AUTHOR [+2]

Abstract

Disclosed is a method by which polysilicon resistors may be both fabricated and trimmed late in the device fabrication process, with real-time feedback and tuning of the trim process.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

In Situ-Trimmed Fine-Grained Polysilicon Resistors

       Disclosed is a method by which polysilicon resistors may
be both fabricated and trimmed late in the device fabrication
process, with real-time feedback and tuning of the trim process.

      The use of polysilicon load resistors in integrated circuits
offers potentially significant performance enhancement due to the
reduction in parasitic capacitance and resistor layout area relative
to implanted single crystal resistors.  In order to realize this
potential, however, it is necessary to accurately control the
resistivity of the heavily doped polysilicon films.  This is an
inherently difficult task since the polysilicon resistivity depends
strongly on grain size, grain texture, dopant incorporation, dopant
activation and dopant segregation, all of which may vary during
processing.  This article describes a novel fabrication method for
such resistors, combining tight control of starting materials with a
method for the monitored trimming of such materials to a high degree
of precision.

      In this embodiment, UHV/CVD (*) is employed to deposit
fine-grained polysilicon films whose resistivity is controlled to
result in a layer with a sheet resistance which is below the desired
value by an amount equal to the maximum observed variation between
wafers within a run and wafers run to run.  As an example, if sheet
resistivities vary 6 percent within a single deposition run, but 10
percent run to run, all depositions would be targeted to produce
material whose sheet resistivities fall 10 percent below the desired
result.

      These in-situ doped polysilicon layers would first be inspected
to ascertain the exact sheet resistivity.  They would then be trimmed
to the desi...