Browse Prior Art Database

Yield, Reliability, SPQL And Delay Monitoring Structures On Product Chips

IP.com Disclosure Number: IPCOM000102084D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 96K

Publishing Venue

IBM

Related People

Magdo, S: AUTHOR

Abstract

Yield monitoring test site (YMTS) chips currently used for yield/defect analyses of semiconductor wafers occupy chip sites that would otherwise be available for product chips, thereby reducing product yields. This article describes the employment of presently "unused" portions of logic and array product chip "real estate" to perform yield/defect analyses, thereby eliminating unnecessary YMTS chip substitution activity, and contributing to an increase in usable product chips obtained per wafer processed.

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Yield, Reliability, SPQL And Delay Monitoring Structures On Product Chips

       Yield monitoring test site (YMTS) chips currently used
for yield/defect analyses of semiconductor wafers occupy chip sites
that would otherwise be available for product chips, thereby reducing
product yields.  This article describes the employment of presently
"unused" portions of logic and array product chip "real estate" to
perform yield/defect analyses, thereby eliminating unnecessary YMTS
chip substitution activity, and contributing to an increase in usable
product chips obtained per wafer processed.

      Logic chips are the best candidates for including different
test structures in their design.  A maximum of 90% of their circuits
(average N60%) are wired up (used), leaving the number of unused
circuits available for incorporating test structures in the range of
several hundred to several thousand.  These can be wired up as shown
below.

                            (Image Omitted)

      Direct circuit (stage) delay information is not presently
available on logic chips .  Nominal delay per stage values are now
established by means of modeling and test chips.  On each wafer the
ring oscillators are tested on the test sites and, based on the test
data, the whole wafer is either accepted or rejected for compliance
with the delay requirement.  Such a test does not, however, give
information about delay variations on the wafer and between wafers.
Tracking between chips is also unknown.  Critical path delays must
therefore be calculated by the system designer on the basis of
certain assumptions.  Present pass and fail criteria for delay acts
to lower the SPQL (shipped product quality level) since some passing
chips will fail in the system and some good chips will be rejected,
thereby lowering the yield.

      By monitoring the delay on each chip, additional delay can be
eliminated, allowing critical path delays to be reduced N12%, and
chips to be selected for delay, with resultant improvement in SPQL.
This additional delay was added to each critical path delay since it
was assumed that tracking between chips is 50 10.  By way of example,
some of the ring oscillators and inverter chains (see above
illustration) would be powered up dur...