Browse Prior Art Database

Dual-chained Control Block Data Structure With Synonymous Logical and Physical Chains

IP.com Disclosure Number: IPCOM000102097D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 6 page(s) / 179K

Publishing Venue

IBM

Related People

Dayan, RA: AUTHOR [+5]

Abstract

A method and hardware implementation is described whereby computer systems equipped with bus master adapters are provided with a dual- chained control block data structure with synonymous logical and physical chains.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dual-chained Control Block Data Structure With Synonymous Logical and Physical Chains

       A method and hardware implementation is described whereby
computer systems equipped with bus master adapters are provided with
a dual- chained control block data structure with synonymous logical
and physical chains.

      Computer systems equipped with bus master adapters which have
the ability to process a chain of control blocks, such as small
computer system interface (SCSI) hardware attachments, allow chaining
of subsystem control blocks (SCBs) through physical addresses.
However, systems which function with the advanced basic input/output
system (ABIOS) require logical addresses to access the SCBs and
associated termination status blocks (TSBs) for appropriate action
when an error occurs.  The concept described herein allows the
operating system to utilize SCB chaining while receiving high level
error recovery, similar to that which is available for ABIOS
functions.

      Generally, SCSI hardware attachments provide a high-performance
command interface via SCB chaining.  The SCSI BIOS programs the
attachment with a thirty-two bit physical pointer which identifies
the SCB to be processed.  Within each SCB is an optional physical
pointer to another SCB which is processed upon successful completion
of the current SCB.  This forms the basis for the existing physical
SCB chain.  Also, within each SCB is a physical pointer to the TSB
where information detailing the completion of the SCB is stored by
the attachment.

      Building of SCBs outside of the domain of ABIOS can require
high- level error recovery outside of ABIOS.  This can result in code
duplication as well as losing some insulation of the underlying
hardware, as is provided by ABIOS for existing functions, such as
read and write disk blocks.  ABIOS, due to the microprocessor
addressing mechanism, requires logical addresses of pointers in order
to access fields within either the SCB or the TSB.  The physical
addresses required by the attachment for chaining of the SCBs cannot
be used by the system micro processor to access SCB chains in memory.
If physical addresses are used, a protection violation occurs in
protect mode operation of the microprocessor.  Access in real mode
might cause incorrect data to be read or written.  As a result, a
method is required to provide an ABIOS interface to allow use of SCB
chaining by disk device drivers.  Also, required is ABIOS access to
SCBs and TSBs to read pertinent status information and to provide the
necessary error recovery.

      The method used in the concept is to build a logical address
chain to coincide with the SCB chain in memory.  A chain header
element is attached to the front of each SCB that logically links
SCBs togeth...