Browse Prior Art Database

Reducing I/O Requirements With Compare Logic

IP.com Disclosure Number: IPCOM000102111D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Lusch, RF: AUTHOR [+2]

Abstract

Disclosed is a technique that uses a compare circuit to reduce the number of I/O pins required when testing logic devices.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Reducing I/O Requirements With Compare Logic

       Disclosed is a technique that uses a compare circuit to
reduce the number of I/O pins required when testing logic devices.

      A typical embodiment of this technique involves the testing of
an array which is embedded within a logic assembly.  Generally, not
all of the array inputs and outputs are visible at the boundary of
the assembly due to I/O constraints.  Hence, direct access to the
array for testing purposes is not possible.

      The high level diagram of the disclosed technique is shown in
the figure.  The left side of the figure shows the array component
with its control lines, address lines, data input lines, and data
output lines.  The right side depicts the compare circuit, which may
be existing functional logic or may be logic added specifically for
test purposes.  One input to the compare is the output data of the
array; the other is the same input data that feeds the array
component. It is assumed that the DATAOUT lines from the array are
not easily accessible by the tester because of I/O constraints and
that the compare output represents a fewer number of output lines
than the DATAOUT bus.

      With this configuration, the array is loaded during testing in
the usual manner by selecting an address, placing the desired data
pattern on the DATAIN lines, and activating the proper controls to
perform the write operation. However, when the array is to be read
out and checked during the...