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Browse Prior Art Database

Coupled Compensator

IP.com Disclosure Number: IPCOM000102115D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Commander, RD: AUTHOR

Abstract

This article describes a solution to a problem encountered during the design of an Actuator Driver on a magnetic disk file. It allows a reduction in time delay of polarity reversal in single-ended I/P or magnitude/polarity controlled Linear Power Driver.

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Coupled Compensator

       This article describes a solution to a problem
encountered during the design of an Actuator Driver on a magnetic
disk file.  It allows a reduction in time delay of polarity reversal
in single-ended I/P or magnitude/polarity controlled Linear Power
Driver.

      The diagram shows the essential components of the circuit.  The
file is limited to power supplies of +5V and +12V only.  The value of
the desired load current (

ANALOG DRIVE

) is a positive voltage
referred to ground, and its polarity is a separate logic line.  Load
current of positive polarity is supplied by turning on PFET P2 and
NFET N1, negative load current is provided via P1, N2.  Both PFETs
operate as switches, being either saturated or off.  The NFETS N1, N2
operate in linear mode under control of op amps A1, A2, respectively.
Op amp is enabled by not pulling up A1 -ve input with the CONTROL
block O/P.  A1 and N1 then function as a closed loop current
amplifier.  LOAD current is sensed in RS, while feedback through R5
forces the voltage at the top of RS to be equal to ANALOG DRIVE.  The
large FET capacitances (Cgs and Cdg) introduce a large phase lag and,
hence, instability into this closed-loop amplifier. The FET
capacitance is decoupled from A1 by R3, and the FET is bypassed at
high frequencies by R1, C1 stabilizing the loop.  However, it
introduces a delay where the polarity is reversed.  When current goes
from negative to positive (N1 coming on), the left hand...