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High-Gain Nor Logic Circuit

IP.com Disclosure Number: IPCOM000102121D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Michail, MS: AUTHOR [+2]

Abstract

A new high-gain, high-speed, and relative low-power bipolar logic circuit is shown in the figure. It utilizes fast PNP bipolar transistors. The circuit shown uses four NPN transistors, two vertical PNP transistors, and four resistors. A "bypass" capacitor may be used to speed up the circuit. These devices are used to implement a 3-input NOR gate. The circuit is made up of two sections. The basic NOR circuit on the left establishes the DC levels; the emitter follower on the right drives the cell-to-cell wiring and allows for emitter dotting.

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High-Gain Nor Logic Circuit

       A new high-gain, high-speed, and relative low-power
bipolar logic circuit is shown in the figure.  It utilizes fast PNP
bipolar transistors.  The circuit shown uses four NPN transistors,
two vertical PNP transistors, and four resistors.  A "bypass"
capacitor may be used to speed up the circuit.  These devices are
used to implement a 3-input NOR gate.  The circuit is made up of two
sections.  The basic NOR circuit on the left establishes the DC
levels; the emitter follower on the right drives the cell-to-cell
wiring and allows for emitter dotting.

      The high level output at node A is basically determined by the
power supply Vcc.  The low level output is established when one or
more of the input transistors T1, T2 and T3 is on (i.e., high input).
It is determined by the power supply voltage and the voltage drop
across resistor R1, i.e., (Vcc-IcR1), where Ic is the collector
current of the conducting input transistors.  Ic is controlled by the
fast vertical PNP transistor T4.  The low impedance of the active
device T4 makes this circuit high gain.  Gain is determined by the
ratio of resistor R1 to the effective impedance of the active
transistor T4.

      The logic voltage swing is maintained constant by utilizing the
vertical PNP transistor T5 as a feedback to develop voltage drop
across resistor R3, enough to keep transistor T4 conducting when the
cell input is high.  To explain the feedback mechanism, assume t...