Browse Prior Art Database

Service Functions Through LSSD Mechanism

IP.com Disclosure Number: IPCOM000102123D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 108K

Publishing Venue

IBM

Related People

Orsatti, D: AUTHOR [+3]

Abstract

Disclosed is a fault reporting and command setting mechanism for a data transmission system in which a lot of information has to be exchanged and cannot be supported by a parallel interface.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Service Functions Through LSSD Mechanism

       Disclosed is a fault reporting and command setting
mechanism for a data transmission system in which a lot of
information has to be exchanged and cannot be supported by a parallel
interface.

      It is an extended application of the SELF TEST mechanism
already implemented and which allows to configurate the chips latches
in a unique serial LSSD (level-sensitive scan design) path, then to
build a constant signature in a dedicated register of each chip by
controlling five tags and three clocks. Fig. 1 describes the SELF
TEST (ST) operation.

      When the ST sequence is achieved, the ST controller (STC)
generates another tag pattern to chip to change the chip latch
configuration and place only the chip's signature registers in the
LSSD path.  Then, the STC controller generates a sufficient number of
clocks to shift the chips signatures and get them for checking.
      Fig. 2 shows the signature read configuration.

      This disclosure consists of using some new tag patterns of the
self-test mechanism in order to configurate one or more chips in a
convenient LSSD latch string as described in the following with
reference to Figs. 3, 4 and 5.
 Two additional TAG codes are created called code 1 and code 2.

      When code 1 is sent to the various chips, they all connect a
register called "Exchange register" (ER), made of 2 fields "command"
and "check report", between their Scan IN (SI) and Scan OUT (SO) and
disable the functional clocks of the above mentioned register, the
LSSD clocks being active.

      The whole chips except the "Exchange Registers" remain
functional.  Once this is done, a new chain connecting the "Exchange
Registers" of all the chips is created and connected to STC Scan IN
and Scan OUT.

      In the STC, Scan IN...