Browse Prior Art Database

High Speed Word Recognizer for a Serial Shift Register

IP.com Disclosure Number: IPCOM000102132D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Deremer, RL: AUTHOR [+4]

Abstract

When data words (bytes) are encoded and time-division multiplexed (TDM) into a serial stream of data, a unique word (byte sync word) that is assured not to be a conjunction of two words must be provided. This permits the circuit that receives the data to demultiplex whole words that are not fragmented (conjunctions of two transmitted words).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

High Speed Word Recognizer for a Serial Shift Register

       When data words (bytes) are encoded and time-division
multiplexed (TDM) into a serial stream of data, a unique word (byte
sync word) that is assured not to be a conjunction of two words must
be provided.  This permits the circuit that receives the data to
demultiplex whole words that are not fragmented (conjunctions of two
transmitted words).

      The block diagram and timing diagram for the demultiplexing
logic is shown in Fig. 1.  A phase-locked loop (PLL) realizes the
phase orientation between the clock and serial data.

      The clock and data are fed to a rising-edge triggered 11 bit
shift register.  The shift register consists of 11 differential
positive transition D type master slave flip-flops.

      Upon loading the byte sync word into the first 10 bits of the
shift register, the byte sync detector sends a pulse to the decade
counter.  The byte sync word is a unique word that is assured not to
be a conjunction of two words.  The byte sync detector is a 10-input
OR gate with a reference in the center of the digital voltage swing.
The schematic for the byte synch detector is shown in Fig. 2.

      The decade counter is set on the next rising-edge of the clock.
This rising-edge also shifts the data one bit in the shift register.
The block diagram and timing diagram for the decade counter is shown
in Fig. 3.  The decade counter is a Johnson counter with state
correction.  The...