Browse Prior Art Database

Multi-Shell Trench Capacitor Cell for Quarter Giga Bit DRAM and Beyond

IP.com Disclosure Number: IPCOM000102162D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Hsu, CH: AUTHOR [+2]

Abstract

Disclosed is a fabrication method for making a new Multi-Shell Trench (MST) capacitor cell for quarter giga bit DRAM and beyond.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Multi-Shell Trench Capacitor Cell for Quarter Giga Bit DRAM and Beyond

       Disclosed is a fabrication method for making a new
Multi-Shell Trench (MST) capacitor cell for quarter giga bit DRAM and
beyond.

      As the density of DRAM increases, the cell size has to be
shrunk.  Consequently, the capacitance of the DRAM cell, which
governs the figure of merit of DRAM performance, decreases and the
performance of DRAM degrades rapidly due to smaller signal and less
noise margin.

      MST capacitor cell, shown in this disclosure, serves to
significantly increase the storage capacitance with a shrunk cell
size.  This capacitor cell is fabricated utilizing a chemical vapor
deposition (CVD) epitaxial technique to grow intrinsic and p + Si
layers alternatively.  A preferential wet etch process is employed to
remove the intrinsic Si (i-Si) layer and leaves the p + Si shells in
the deep trench.  Thin oxide/nitride/oxide layers are then formed as
a dielectric film of the capacitor.  The trench is finally filled
with p polysilicon to form a MST capacitor cell.  The fabrication
processes are shown in Figs. 1 to 5.