Browse Prior Art Database

Command Mailbox Sequencing

IP.com Disclosure Number: IPCOM000102177D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Irwin, JW: AUTHOR

Abstract

A method is described by which command mailboxes can be issued by a device driver 2 across an I/O bus 3 to an I/O adapter. The advantages of this method are simplified processing within the adapter and inherent checking of hardware and microcode.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Command Mailbox Sequencing

       A method is described by which command mailboxes can be
issued by a device driver 2 across an I/O bus 3 to an I/O adapter.
The advantages of this method are simplified processing within the
adapter and inherent checking of hardware and microcode.

      A hardware environment is shown in the figure which is
unchanged between the prior art and the improved method. The
invention is embodied in the Device Driver host code 2 and the
adapter microcode as hereafter described.

      The host system 1 issues each command as a 32-byte mailbox
which is copied to the adapter mailboxes 4 by a Programmed
Input/Output (PIO).  It is a requirement that strict ordering of
mailboxes be preserved.  The target offset in the adapter RAM is
associated with an 8-bit "tag" used within the adapter to identify
the mailbox. Adapter hardware 5, on receiving the mailbox PIO, sets a
positional bit in a 32-bit adapter register 6 according to the target
offset.  The adapter microprocessor 8 is then informed by an
interrupt that a mailbox has been written, and upon sampling the
bitmap and converting the set bit to an 8-bit value, knows which
mailbox to execute in the RAM 9.  At completion of the command, a
separate set of registers is used to inform the host that the command
is complete.  At this time, the released tag is returned to the
available queue in the host.

      The above sequence works so long as the adapter microcode can
keep ahead of the host issuing mailboxes. However, when more than one
bit is set in the register, the microcode has no way of knowing the
sequence of mailbox issuance.  In an actual adapter, the host often
writes a number of mailboxes before the adapter microcode can respond
to the first interrupt.

      An i...