Browse Prior Art Database

Parallel Preaccess of Two Resolved Addresses From One-port Array

IP.com Disclosure Number: IPCOM000102183D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Irish, JD: AUTHOR [+2]

Abstract

In a given processor, an array may be provided for storing Virtual and Real Addresses of operands in a processor instruction. Generally, the Virtual and Real Addresses of an operand are accessed together. However, in two operands, storage-to-storage instructions, it may be desirable to preaccess the Real Addresses for both of the operands in parallel at the beginning of a processor cycle, and select between them at the very end of the processor cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parallel Preaccess of Two Resolved Addresses From One-port Array

       In a given processor, an array may be provided for
storing Virtual and Real Addresses of operands in a processor
instruction.  Generally, the Virtual and Real Addresses of an operand
are accessed together.  However, in two operands, storage-to-storage
instructions, it may be desirable to preaccess the Real Addresses for
both of the operands in parallel at the beginning of a processor
cycle, and select between them at the very end of the processor
cycle.

      This article describes a method that allows the operand
addresses to be accessed in both of the above configurations using a
single read port array.

      For the purposes of this article, assume a given processor
contains an array for storing Virtual and Real Addresses.  This array
has a single read port.  The format of the data stored in the array
is shown in Fig. 1.

      In the processor's handling of two operands, storage-to-storage
instructions, the processor must operate on the operand data, and
then decide what kind of storage access is required next.  The
storage access could be to fetch more data for one of the operands or
store data from one of the operands.  The sequence of events from the
processor's decision to the actual access of storage being started
would be that shown in Fig. 2.

      A cycle could be saved if both operands' Real Addresses could
be accessed from the array during Cycle 1 and selected at the end of
that cycle, allowing the storage access to be started in Cycle 2.

      The method used allows a single read port array to be...