InnovationQ will be updated on Sunday, Jan. 21, from 9am - 11am ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Address Compare Synchronization

IP.com Disclosure Number: IPCOM000102189D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 120K

Publishing Venue


Related People

Knipfer, DL: AUTHOR [+3]


Disclosed is a method for synchronizing the setting of Address Compares in a multiprocessor system. Address Compares are used to detect when an access (i.e., fetch or store) to main store occurs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Address Compare Synchronization

       Disclosed is a method for synchronizing the setting of
Address Compares in a multiprocessor system.  Address Compares are
used to detect when an access (i.e., fetch or store) to main store

      The address compare mechanism works via a combination of
hardware and microcode.  When an address compare is set, it is
logically in effect across the entire system.  Each processor has
independent physical address compare facilities.  The microcode is
responsible for communicating changes in address compare settings to
all processors and synchronizing the independent physical hardware to
provide a single logical facility.  An address compare control block
contains the compare address and information about the type of
compare set.  Some of this data is used to set a hardware register,
which is used by the hardware to monitor all main store accesses, and
some of it is used by microcode to determine more about the address
compare.  This control block can specify a number of different types
of Address Compares, such as compare on I/O accesses, instruction
fetches, or operand stores.  It is also possible to specify a data
byte for comparing against the data stored to the address.

      If an access of this type occurs, and at the address specified
in the address compare register, the hardware signals the microcode
and sets an address compare occurrence bit.  This causes control to
be passed to a microcode exception handler.

      The microcode in the exception handler then further
interrogates the hardware detected address compare (for example, by
manually checking the data in main store versus the data compare
byte).  If the address compare criteria are met, an address compare
is presented.  If not, the address compare is suppressed.

      Address compares could be reported erroneously if the physical
address compare hardware registers on each processor were out of sync
with the logical system address compare setting.  If one processor
changes the address compare control block after another processor's
hardware has detected an address compare and set the occurrence bit,
but before the microcode has had a chance to interrogate it further,
the control block used for this interrogation will not correspond to
the address compare detected by the hardware.  The compare
subsequently reported will be erroneous.

      Consider the following scenario:
PROCESSOR 1                         PROCESSOR 2
Detects address compare on Address A and sets address compare
occurrence bit
 Alters address compare setting from Address A to Address B and
updates the control block
Interrogates the address compare on Address A using the control block
for Address B

      Initially the address compare hardware registers on all
processors and control blocks are set to compare on Address A.  The
hardware on Processor 1 detects that an access has occurred, sets its