Browse Prior Art Database

Vertical Parity Correction

IP.com Disclosure Number: IPCOM000102198D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Burton, RWB: AUTHOR [+2]

Abstract

When accessing memory, usually some type of error detection and correction scheme is used to correct memory errors. The common method of error detection is to use horizontal parity, and when a parity error is detected, an error correction algorithm is used. Horizontal parity usually has one parity bit for each byte of a word. One error correction algorithm that can be used is vertical parity correction. Disclosed is a vertical parity correction and how it is used to correct memory errors using the same data registers used when normally accessing the data.

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Vertical Parity Correction

       When accessing memory, usually some type of error
detection and correction scheme is used to correct memory errors.
The common method of error detection is to use horizontal parity, and
when a parity error is detected, an error correction algorithm is
used.  Horizontal parity usually has one parity bit for each byte of
a word.  One error correction algorithm that can be used is vertical
parity correction. Disclosed is a vertical parity correction and how
it is used to correct memory errors using the same data registers
used when normally accessing the data.

      To use vertical parity correction, memory should be divided up
into blocks of memory.  Each block of memory would have one vertical
parity word.  Each bit of the vertical parity word is parity of the
column of data within that block.  Fig. 1 illustrates how the memory
and the vertical parity word should be organized.  The vertical
parity word does not have to be the last word but can be anywhere
within the block of memory.

      When in the normal run state (RS), memory is read into a data
register where parity is checked.  If the parity is good, the data
will be processed.  If a parity error is detected, the logic will go
into an error correction state (ECS).  When in this state, the block
of memory which contains the bad word is read back through the data
register. As the memory is read, it is EXCLUSIVE ORed with the data
in the data register.  See Figs....