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Frequency Synchronization Method for Switched-Mode Power Converters

IP.com Disclosure Number: IPCOM000102216D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Erich, SY: AUTHOR [+2]

Abstract

Disclosed is a circuit technique to achieve frequency synchronization of Pulse Width Modulated (PWM) oscillators that generate timing signals by charging a capacitor from a current source and then releasing a clock pulse when the capacitor voltage reaches a threshold.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Frequency Synchronization Method for Switched-Mode Power Converters

       Disclosed is a circuit technique to achieve frequency
synchronization of Pulse Width Modulated (PWM) oscillators that
generate timing signals by charging a capacitor from a current source
and then releasing a clock pulse when the capacitor voltage reaches a
threshold.

      This method synchronizes multiple controllers to the one which
operates at the highest frequency.  Selected values of a timing
capacitor (Ct) and a timing resistor (Rt) determine the frequency of
operation of the controller. However, even if all controllers in a
system use identical circuitry, the oscillator frequencies will not
be the same because of the tolerance variation in the values of Rt
and Ct.

      The controller operating at the highest frequency charges its
timing capacitor faster than the other controllers.  When this
controller's capacitor voltage reaches its upper threshold, a pulse
is released through a driver onto a single interconnecting line, the
synch bus (see figure). The other receivers accept this pulse and use
it to switch a current source into the circuit to inject additional
current into their timing capacitors, so that the capacitor voltages
reach their upper thresholds at a faster rate.  Once this threshold
is reached, the capacitor is rapidly discharged to a lower threshold,
which initiates a new PWM cycle.  This early termination of the PWM
cycle locks their frequency to that of the...