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Recovering From Soft Errors in Translate Control Store

IP.com Disclosure Number: IPCOM000102231D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 117K

Publishing Venue

IBM

Related People

Irish, JD: AUTHOR

Abstract

Described is a mechanism for recovering from soft errors in the memory array that holds Translate Control Words. The Translate Control Words are microcode words that control the Effective Address Generation and Cache Access stages of a given processor pipeline.

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This is the abbreviated version, containing approximately 51% of the total text.

Recovering From Soft Errors in Translate Control Store

       Described is a mechanism for recovering from soft errors
in the memory array that holds Translate Control Words.  The
Translate Control Words are microcode words that control the
Effective Address Generation and Cache Access stages of a given
processor pipeline.

      In a given processor, the execution of instructions can be
pipelined.  The following is a brief description of assumed processor
pipeline stages and their functions.

      The pipeline that is implemented in the processor is comprised
of four stages:
      1.  Effective Address Generation/Translation
      2.  Cache Access
      3.  Instruction Execution
      4.  Cache Store

      The Effective Address Generation/Translation stage partially
decodes the instruction and calculates the Effective Virtual Address
of one of the operands of the instruction.  It then translates this
address into a Real Main Store Address through a Translation
Lookaside Buffer. This cycle also fetches the microcode control word
that will determine what is done in the Cache Access Stage.  This
control word is referred to as a Translate Control Word.

      The Cache Access stage decodes the Translate Control Word and
then fetches the operand whose address was calculated in the previous
stage.  The Cache Access stage may require one or more cycles to
perform the cache fetch. In addition, there is a requirement that all
previous instructions in the pipeline have finished the Cache Store
stage (if they use it) before the fetch in the Cache Access stage can
be executed.  This guarantees that the Cache Access stage fetch gets
the latest data in the case that the Cache Store stage is altering
the same cache address.

      The Instruction Execution stage executes the Microcode Control
Words that interpret the processor instruction.

      The Cache Store stage performs the store to the cache and main
store of the results of the instruction.  This stage is only used for
instructions that alter main storage.

      It is possible for the memory array used to store the Translate
Control Words in the processor to have a small but measurable soft
error rate.  If a soft error occurs in the Translate Control Store
array, a parity error will be detected when the location with the
error is read during the Effective Address Generation stage of the
pipeline.  In the general case, this parity error will cause an
immediate machine check.  This machine check will halt the system and
require it to be IPLed to be restarted.

      The following is a mechanism whereby the soft error in the
Translate Control Store (TCS) can be recovered from without halting
the system.  The method used is to synchronize the reporting of the
Translate Control Store Parity Error, caused by the soft error, with
an instruction boundary.  In particular, all instructions in the
pipeline that precede the instructio...