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Write Protection Circuit for Eeros On an I/O Subsystem

IP.com Disclosure Number: IPCOM000102237D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 155K

Publishing Venue

IBM

Related People

Padgett, RS: AUTHOR

Abstract

This article describes circuitry in a computer system I/O subsystem which provides write protection for electronically erasable read-only storage (EEROS) during updating.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Write Protection Circuit for Eeros On an I/O Subsystem

       This article describes circuitry in a computer system I/O
subsystem which provides write protection for electronically erasable
read-only storage (EEROS) during updating.

      In some computer systems most of the I/O subsystem cards use an
EEROS which contains all of the power on diagnostics, vital product
data (VPD), and some operational code.  These EEROS modules can be
updated in the field to reflect the latest level of code as it
becomes available to the users.  However, if during an update, a
power glitch, a power-on reset, or a miscode of some type were to
happen, the EEROS is destroyed.  There is no way to update it in the
field so the card has to be pulled.  The circuit disclosed herein
alleviates this problem by guaranteeing data integrity.

      Fig. 1 is a functional block diagram of this circuit. The COPY
SEL A line may be generated in a number of different ways via another
EEROS or an erasable programmable logic array (PLA).  No matter how
the line is generated, it must be capable of changing polarity upon
programming and then maintaining that state until it is programmed
again. Fig. 2 is one possible circuit that could be used.  The EEROS
active pin is always active so that the copy bit will be on unless a
write copy bit operation is being done.

      Referring to Fig. 1, the circuit operation for READS is as
follows:
      1.   At power-up time the COPY SEL line A will be at a
predetermined value (to be explained later).
      2.   When an EEROS SEL B is generated, if the COPY SEL A line
is active high, AND gate 3 will be enabled and output C will go
active high.  This will enable OR gate 6, and output D will go active
high selecting EEROS copy 1.
      3.   If the WRITE EEROS E line is inactive, inverter 9 will
cause output F to go high.  F going high along with EEROS SEL B will
cause AND gate 4 to be enabled and output G will go active which will
enable EEROS copy 1 data outputs.  This is because it is the one
which has an active select line.
      4.   When an EEROS SEL B is generated, if the COPY SEL A line
is active high, AND gate 5 will be disabled and output L will go
inactive low.  This will disable OR gate 7, and output M will go
inactive low, causing EEROS copy 2 not to be selected.
      5.   When an EEROS SEL B is generated, if the COPY SEL A line
is inactive low, inverter 8 will cause output K to go high and AND
gate 5 will be enabled and output L will go active high.  This will
enable OR gate 7 and output M will go active high selecting EEROS
copy 2.
      6.   If the WRITE EEROS E line is inactive, inverter 9 will
cause output F to go high.  F going high along with EEROS SEL B will
cause AND gate 4 to be enabled and output G will go active which will
enable the EEROS copy 2 data outputs.  This is because it is the one
which has an active select line.
      7.   When an...